1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a test function in a multi-bank 2-port memory device.
2. Description of the Related Art
In image processing, for example, a memory requires unbroken, continuous read/write operations and concurrent processing such as bank activation and precharge.
A general 1-port multi-bank memory has one port, which comprises control lines for feeding bank active, bank precharge, read, write, row address and column address signals, and data lines for feeding read data and write data. This configuration allows only one command to enter in an identical cycle. Accordingly, it is not possible to execute read and write operations at the same time.
On the other hand, a 2-port multi-bank memory has two ports each provided with respective bank active, bank precharge, read, write, row address and column address control lines. Therefore, it is possible to feed plural commands in an identical cycle and execute read and write operations at the same time.
As obvious from the above, because the 2-port multi-bank memory can support image processing and so forth by one piece, it is more advantageous in cost and so forth than the 1-port multi-bank memory (Patent Document 1: JP 5-109279A).
The existing test systems (hereinafter referred to as “general memory testers”) owned by the semiconductor memory manufacturers have been produced for the purpose of testing 1-port memories in many cases and are difficult to test 2-port multi-bank memories sufficiently based on the actual specs for the following reasons.
Firstly, the general memory tester can not generate plural different addresses at the same time even when it is required to feed different addresses to 2 ports individually in a test on concurrent read/write operations and so forth.
Secondly, it is only possible to generate identical write data and expected-value data (read data) at the same time.